This invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off. There are several different types of nonvolatile memories including erasable programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories. EPROMs are erasable through light exposure but are electrically programmable by channel hot electron injection onto a floating gate. Conventional EEPROMs have the same programming functionality, but instead of being light erasable they can be erased and programmed by electron tunneling. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques. Flash EEPROMs may be block erased, typically giving them better read access times than regular EEPROMs.
Currently, flash memories have gained considerable popularity. For example, flash memories are often utilized to provide on-chip memory for microcontrollers, modem and SMART cards and the like where it is desirable to store codes that may need fast updating.
While flash memories and EEPROMs are closely related, in many instances flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
When EEPROMs are erased, one or more of cells are erased in one operation. A high positive potential is applied to the cell sources and/or drain while the control electrode and the substrate are grounded. As a result, negative charges on the floating gate are drawn to the source and/or drain region by Fowler-Nordheim tunneling. This technique is effective where the dielectric between the floating gate electrode and the source and/or drain regions is very thin.
A number of disadvantages arise from the conventional erasing technique, including the fact that it creates the possibility of a reverse voltage breakdown between the source and/or drain and substrate junctions which would cause hot hole trapping in oxide and reliability problems. Chi Chang, et al. "Drain Avalanche and Hole Trapping Induced Gate Leakage in Thin Oxide MOS Devices," IEEE Electron Device Letters, Vol. 9, 1988, pp. 588-90. To overcome this, some designers have used a so-called double diffused junction to enhance the junction substrate breakdown voltage. However, the double diffused junction has certain disadvantages, including (1) the fact that it may require additional cell size, reducing the potential cell density and (2) it still has Gate Induced Drain Leakage (GIDL) current. Another potential solution is the use of relatively high negative potentials on the control gate and hence less voltage is applied to the source. Sameer S. Haddad et al. U.S. Pat. No. 5,077,691 titled, "Flash EEPROM Array with Negative Gate Voltage Erase Operation." This in turn would reduce the field across the source to substrate junction.
However, as channel lengths become small this hole trapping becomes channel length dependent. This effect has been described as a possible "fundamental limitation to the scaling of flash memory cells". Jian Chen, et al., "Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell", IEDM 1995 - 331, 13.6.1-13.6.4. That article indicates that during the discharge stress, the holes generated from band-to-band tunneling travel through the silicon-to-silicon dioxide interface, are accelerated by the strong lateral electric field, and gain sufficient energy to become energetic hot holes. The article explains that a negative gate voltage pulls these energetic hot holes to the gate causing them to bombard the surface, get trapped and create interface states. As channel length decreases, the lateral field increases, exacerbating the effect.
The article suggests that the problem may be avoided by increasing the channel length. Since this solution is counter to the longstanding industry trend of scaling devices to increasingly smaller and smaller sizes resulting in lower cost products in smaller dimensions, this solution is not particularly desirable. Chen, et al. suggests that another solution to the problem is to apply a positive bias to the drain while discharging the cell from the source node. While the results discussed in the article indicate that this does improve the problem to a certain degree, some of the degradation appears to remain, even when this approach is used.
It has also been suggested that using channel erase with a large negative voltage applied to the control gate and a voltage of five volts applied to a P-well and an N-well could improve gate disturb tolerance and reliability due to the decrease in hot hole generation near the source region. See, T. Jinbo, et al., "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode", 1992 IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992 at pages 1547-1554. This requires a negative gate voltage that is about 1/3 higher than that in the drain erasure situation (the Haddad, et al. U.S. Pat. No. 5,077,691). See, Hsing-jen Wan, et at., "Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction," Proc. of IEEE VLSI Technology Symposium (Japan) May 1993, p. 81-2.
The inventor of the present invention believes that none of these approaches is fully satisfactory and that there is a continuing need for an efficient, scalable erase mechanism. Thus, while those skilled in this art have appreciated a number of advantages that could accrue from the use of a negative control gate potential in connection with EEPROM erase cycles, a variety of deficiencies have discouraged those of skill in this art from pursuing those advantages.